Double-data-rate (DDR) dynamic random access memory (DRAM) is a high performance, low-cost memory. DDR capture registers and half-data-rate (HDR) registers allow safe transfer of data from the DDR domain (data on both edges of clock) down to the single data rate (SDR) domain (data on positive edge of clock, but at twice the data width) down to HDR domain where data on positive edge of clock, but the frequency is now half that of the SDR, and data width is doubled.
Design of a memory interface from a PLD to an external memory device utilizes many inputs, such as allocation of bandwidth to data ports, buffering requirements, maintaining transaction ordering, trade-offs of buffer depths versus scheduling efficiency versus allowed latency, and packet size of write data. Transactions that must be returned in order at the master interface are referred to as threads in this document. Many or all of these inputs are determined only during the electronic design (the soft-logic portion of the PLD) is made. Thus, memory interface including thread queue systems has been typically implemented in soft-logic.
In other hardware contexts, such as ASICs, thread queue systems used with external memory schedulers do not require the allocation flexibility as those of PLDs because most or all of these inputs are known when the chip is built. For example configuration of queue time sharing between masters or initiators for selecting the available bandwidth from an aggregate master is a function that only occurs after embedded resources in an FPGA are created. A hard-logic implementation of a memory interface structure for an FPGA has to be flexible to cover a variety of possible input values.